1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a ferroelectric film applied to EEPROM (Electrically Erasable/Programmable Read Only Memory), and the like.
2. Description of the Prior Art
When an electric field is applied to a ferroelectric substance like PZT (Lead(Pb) Ziroconate Titanate), for example, a polarization direction is aligned to the direction of the electric field. This state of directional alignment remains after the electric field is dissipated. That is, a polarization of the ferroelectric substance occurs with a hysteresis characteristic when applying an electric field. Thus, such hysteresis characteristic can be utilized to design a nonvolatile memory.
FIG. 8 is a diagram showing the variation in polarization when an electric field is applied to a ferroelectric substance. As the electric field is increasingly applied to the ferroelectric substance, polarization P increases in a direction equivalent to that of the electric field, and when the electric field having E.sub.sat or over in strength is applied, this results in saturation represented by A in FIG. 8. Then, as the electric field is reduced, the polarization P decreases but still remains under zero electric field to make a state represented by B. Moreover, when an electric field in a reverse direction is applied, the polarization P decreases, then it reaches zero under a certain negative electric field. With further application of the reverse electric field, the polarization P increases in the reverse direction, and it assumes saturation represented by C with the applied electric field of more than -E.sub.sat in strength. When the negative electric field is reduced from this saturation state C, the polarization P still remains under zero electric field to make a state represented by D in FIG. 8. Increasing the positive electric field beginning at this state, the polarization P ultimately presents the saturation state A.
Nonvolatile memory devices utilizing such a hysteresis characteristic of ferroelectric substances are disclosed, for example, in "Ferroelectric Chips (VLSI SYSTEM DESIGN, MAY 1988, PP.116-123, S. BAKE)" and Japanese Unexamined Patent Publication No. 201998/1988. Those documents disclose a nonvolatile memory device having a memory cells aligned in a matrix manner, each of which can store one bit of data, and a structure of each memory cell is shown in FIG. 9 herein. The memory cell includes a ferroelectric capacitor 1 and a switching MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 2.
Without application of an electric field, a ferroelectric substance sandwiched between plates of the ferroelectric capacitor 1 presents a state represented by B or D in FIG. 8. The correlations between states B, D and logic status "1" and "0" are predetermined. For example, when the ferroelectric substance presents the state B, applying positive voltage VP in a form of pulse via the switching MOSFET 2 to the capacitor 1 causes almost no current to flow into the capacitor 1. In this situation, the ferroelectric substance temporarily presents the state A and then recovers the state B. Otherwise, when the ferroelectric substance presents the state D, applying the positive voltage VP in the form of pulse to the capacitor 1 causes relatively large current to flow into the capacitor 1. In this situation, the ferroelectric substance temporarily presents the state A and thereafter turns to the state B.
Thus, the amount of the current flowing into the capacitor 1 may be monitored while the switching MOSFET 2 is rendered conductive, so as to find whether the ferroelectric substance between the plates of the capacitor 1 presents the state B or the state D. This allows data stored in the memory cell to be read. Writing or erasing data can be conducted by charging or discharging the capacitor 1 to invert the polarization direction in the ferroelectric substance between the plates of the capacitor 1.
When a reading operation is performed with the ferroelectric substance in the state D, the ferroelectric substance turns to the state B. This means that reading data from the memory cell results in the destruction of the data in the memory cell. For this reason, in the previously mentioned structure, stored data must be regenerated each time data is read out.
As mentioned above, however, by destroying and regenerating data stored in the memory cell whenever data is read therefrom, there arise more inversions of the polarization directions in the ferroelectric substance between the plates of the capacitor 1. As a result, fatigue advances more quickly in the ferroelectric substance, and a less number of times can the data be reloaded. In order to find the current state of the ferroelectric substance based upon the amount of the current flowing into the capacitor 1 when a voltage plus is applied, movement of sufficient electric charges is needed. In other words, it is necessary that the capacitor 1 contains accumulated electric charges (about 30 fF) equivalent to those contained in each memory cell of a DRAM (Dynamic Random Access Memory) in the state B or the state D where residual polarization occurs. This is why the ferroelectric substance of the capacitor 1 requires residual polarization having a a voltage plus to some extent, which, in turn, results in a smaller choice of ferroelectric substances. Furthermore, for the capacitor 1 to have a larger capacity it should have a larger area, and therefore, there lie limitations to the degree to which the above-mentioned memory cells can be miniaturized. Accordingly, it is difficult to use those memory cells to fabricate an integrated memory.
To overcome those disadvantages, there has been proposed a technology that a memory cell contains an MFSFET (Metal Ferroelectric Semiconductor Field Effect Transistor). Such an MFSFET has a sectional configuration as illustrated in FIG. 10. Specifically, a pair of N-type impurity diffusion layers SD are formed at a specified interval in the vicinity of a surface of a P-type silicon substrate SUB so as to be a source and a drain. A ferroelectric gate film 4 is formed in contact with the surface of the substrate SUB between the pair of diffusion layers SD. A conductive thin film 3 is formed on the ferroelectric gate film 4 so as to act as a gate electrode. In this way, an MFS structure, surrounding the ferroelectric gate film 4, is built.
A layer insulating film 5 is formed covering the conductive thin film 3 and the surface of the substrate SUB. Holes are formed in the layer insulating film 5 at upper portions of the diffusion layers SD so as to act as contact holes, through which source and drain electrodes 6 come into contact with the diffusion layers SD.
When a voltage V.sub.max (&gt;0) by which an electric field E.sub.sat or greater in FIG. 8 can be applied to the ferroelectric gate film 4 is applied to the conductive thin film 3, the ferroelectric gate film 4 turns to the state A. In this situation, a channel connecting the pair of diffusion layers SD is formed in the surface of the substrate SUB just beneath the ferroelectric gate film 4. After that, turning the voltage at the conductive thin film 3 to zero, causes the ferroelectric gate film 4 to presents the state B in FIG. 8. That is, the channel still lies since polarization remains. Otherwise, when voltage at a level of -V.sub.max is applied to the conductive thin film 3 (or when the voltage of +V.sub.max is applied to the substrate), the ferroelectric gate film 4 turns to the state C. While it turns to the state C, the channel dissipates. Then, when voltage applied to the conductive thin film 3 is zero, the ferroelectric gate film 4 turns to the state D. While it is in the state D, the channel still dissipates.
Thus, if appearance and disappearance of the channel are related so as to correspond to logical status "0" and "1", respectively, nonvolatile storage can be constructed. Since reading of stored data can be performed by checking whether the MFSFET is conductive or a non-conductive, reading operation can be performed without the destruction of the stored data. Accordingly, this MFSFET, if applied to a memory cell, the number of times it may reloaded, compared with the memory cell shown in FIG. 9.
Residual polarization required for the ferroelectric gate film 4 to control the existence or non-existence of the channel just beneath the ferroelectric gate film 4 is as relatively small as 1 .mu.C/cm.sup.2 or less. For this reason, there is a large choice of substances suitable for the ferroelectric gate film 4. Simply important is controlling existence or non-existence of the channel between the source and drain, and therefore, the ferroelectric gate film 4 does not have to have a large area, which enables the memory cell to be miniaturized. This eventually enables an integrated memory to be fabricated easily.
An exemplary structure of a memory cell where the MFSFET is used is shown in FIG. 11. In this memory cell, an MFSFET 7 has its source and drain connected to switching MOSFETs 8 and 9 in series, respectively, and these three transistors together constitute a memory cell. The switching MOSFET 8 has its source connected to a bit line BL and has its gate supplied with voltage from a first word line WL1. Moreover, Vcc/2 which is a half of a definite voltage Vcc is applied to a gate of the MFSFET 7 and a drain of the switching MOSFET 9, respectively. When the voltage Vcc/2 is applied between the gate of the MFSFET 7 and a substrate, the polarization direction of ferroelectric gate film contained in the MOSFET 7 can be inverted. Furthermore, the switching MOSFET 9 has its gate supplied with voltage from a second word line WL2.
Japanese Unexamined Patent Publication No. 64993/1990, for example, discloses a nonvolatile memory having such memory cells aligned in a matrix manner on a semiconductor substrate.
Writing and reading in and from such a memory will be described. First, in writing, a potential at the first word line WL1 is set to Vcc to turn ON the MOSFET 8 while a potential at the word line WL 2 is set to ground potential Vss to turn OFF the MOSFET 9. In this state, voltage corresponding to data is applied from the bit line BL to the source of the MFSFET 7 and a semiconductor substrate. For example, when the ground potential is applied to the bit line BL, the voltage Vcc/2 is applied between the gate of the MFSFET and the substrate with the gate being on the positive side. Consequently, an electric field having a direction from the gate to the substrate is applied to a ferroelectric gate film of the MFSFET 7 to align polarization in the ferroelectric gate film the direction of the electric field. Alternatively, when the potential Vcc is applied to the bit line BL, the voltage Vcc/2 is applied between the gate of the MFSFET 7 and the substrate with the substrate being on the positive side. Consequently, an electric field having a direction from the substrate toward the gate is applied to the ferroelectric gate film of the MFSFET 7 to align the polarization in the ferroelectric gate film the direction of the electric field.
Thus, the ferroelectric gate film contained in the MFSFET 7 can be controlled to be in the state B or the state D in FIG. 8 by applying voltage corresponding to data to the bit line BL. In this way, the MFSFET 7 can be switched between conductive and non-conductive states under control so as to execute data writing.
On the other hand, in reading, a potential higher than the potential Vcc/2 is applied in advance to the bit line BL from a precharge circuit (not shown). In this situation, the voltage Vcc is applied to the word lines WL1 and WL2 to turn both of the MOSFETs 8 and 9 ON. At this time, if the MFSFET 7 is in its conductive state, current flows from the bit line through the MOSFET 8, MFSFET 7 and MOSFET 9 to reduce the potential at the bit line BL. If the MFSFET 7 is not conductive, no current flows, and the potential at the bit line BL stays unchanged. Then, a potential variation at the bit line BL is amplified by a sense amplifier (not shown) and then detected so as to execute data reading. In this case, however, disturbance caused by the reading may greatly affect the polarization in the ferroelectric gate film of the MFSFET 7, and in order to avoid this, a precharge level at the bit line BL must be set to a potential close to Vcc/2.
In a nonvolatile memory employing memory cells as described above, voltage for inverting a polarization in the ferroelectric gate film must be applied between the gate of the MFSFET 7 and the semiconductor substrate. For the purpose, a well 7a is formed in each memory cell in arranging the memory cells on the semiconductor substrate. Controlling the potential at the well 7a attains application of an electric field for data writing to the ferroelectric gate film of the MFSFET 7.
In such a structure, however, applying voltage to the well 7a in any of the memory cells selected in advance causes the voltage to slightly be applied to the wells 7a in the remaining memory cells through the semiconductor substrate. This results in an undesirable weak electric field being applied to the ferroelectric gate film of the MFSFET 7 in each of the non-selected memory cells. Such a weak electric field cannot invert the polarization direction in the ferroelectric gate film in the non-selected memory cell but causes the so-called soft write in the non-selected memory cell; that is, a slight change in the polarization in the ferroelectric gate film is caused.
It now is assumed that the MFSFET 7 in the memory cell where the soft write occurs turns ON. Then, in the case where the pair of switching MOSFETs 8 and 9 are made conductive to read data from the memory cell, drain current in the MFSFET 7 is smaller than the ordinary one, and hence the reliability of data reading is accordingly decreased.
In addition to that, the weak voltage applied to the well 7a in the non-selected memory cell is unstable one which depends upon whether data written in the selected memory cell is "1" or "0", and it takes a indefinite value. Thus, there has been no useful way to prevent such soft write in the non-selected memory cell.